The present invention relates to frequency adjustment systems and more particularly to novel electronic solid state apparatus for imparting a phase or frequency delay to an input signal, phase correction being made without danger of introducing abrupt changes in the output frequency by introducing a precise number of very small phase advance or phase retard offsets at a high adjustable repetition rate.
In applications employing high frequency clocks of extremely high precision, such as cesium clocks, for example, it is well-known that the output frequency of such clocks experiences a drift in phase, and it is therefore necessary to periodically introduce a phase shift correction in order to be able to employ such clocks as reliable time standards. Systems presently available for imparting frequency and/or phase offsets of this nature require long warm-up times and are also known to impart spurious shifts in frequency resulting in the introduction of errors which are themselves more significant than the desired phase offset.
One technique for obtaining the desired result is to employ a digital time incrementer which is comprised of a plurality of counter stages, each being capable of counting in binary coded decimal (BCD) fashion, said BCD stages being connected in cascade. A signal applied to the input of the digital time incrementer thus undergoes a divide-by 10.sup.N operation where N is equal to the number of counter stages employed in the digital time incrementer.
Each BCD counter stage is further designed to be forced to a particular BCD count which differs from the normal BCD count in order to obtain the desired phase advance or phase retard operation by altering the number of pulses applied to the BCD counter stage which is necessary to cause the stage to reach a terminal count. Switch means are settable to force the BCD counter stage to the desired phase retard or phase advance condition a predetermined number of times, the maximum number of repetitive operations typically being no greater than 10.sup.6. In the event that a large offset is required, the larger offset is accommodated by forcing the setting of a more significant BCD counter stage such as, for example, the divide-by 10; divide-by 100; divide-by 1,000 or divide-by 10,000 BCD counter stage of the counter, thereby significantly increasing the size of the delay imparted to the output signal, which also undergoes a reduction in frequency as a function of the number of BCD counter stages employed in the counter.
The above technique has been found to have a significant disadvantage in that a phase advance or phase retard step introduced into a more significant BCD counter stage has been found to introduce undesirable abrupt changes of significant magnitude into the output signal which prohibits the use of the digital time incrementer of the type described in high frequency applications requiring smooth transitions in the phase offset. Thus, high frequency generators requiring a large phase adjustment cannot be adjusted satisfactorily through the use of presently-available techniques.